Although they can in principle be applied to any desired integrated circuits, the present invention and the problems on which it is based are explained with reference to integrated memory circuits in silicon technology.
FIG. 1 shows a diagrammatic sectional view through a semiconductor memory cell having a trench capacitor and a planar select transistor connected to it.
In FIG. 1, reference numeral 1 denotes a silicon semiconductor substrate. Trench capacitors GK1, GK2, which have trenches G1, G2 whose electrically conductive fillings 20a, 20b form first capacitor electrodes, are provided in the semiconductor substrate 1. The conductive fillings 20a, 20b are insulated with respect to the semiconductor substrate 1 in the lower and central regions of the trench by a dielectric 30a, 30b, the substrate in turn forming the second capacitor electrodes (if appropriate in the form of a buried plate, which is not shown).
Encircling insulation collars 10a, 10b, above which buried contacts 15a, 15b which are in electrical contact with the conductive fillings 20a, 20b and the adjoining semiconductor substrate 1, are provided in the middle and upper regions of the trenches G1, G2. The buried contacts 15a, 15b are only connected to the semiconductor substrate 1 on one side (cf. FIG. 2a, b). Insulation regions 16a, 16b insulate the other side of the substrate from the buried contacts 15a, 15b and/or insulate the buried contacts 15a, 15b from the top side of the trenches G1, G2.
This allows a very high packing density of the trench capacitors GK1, GK2 and the associated select transistors, which will now be explained. In this context, reference is made primarily to the select transistor which belongs to the trench capacitor GK2, since of adjacent select transistors only the drain region D1 or the source region S3 is included in the drawing. The select transistor belonging to the trench capacitor GK2 has a source region S2, a channel region K2 and a drain region D2. The source region S2 is connected via a bit line contact BLK to a bit line (not shown) arranged above an insulation layer I. On one side, the drain region D2 is connected to the buried contact 15b. A word line WL2, which includes a gate stack GS2 and a gate insulator GI2 surrounding the gate stack, runs above the channel region K2. The word line WL2 is an active word line for the select transistor of the trench capacitor GK2.
Word lines WL1, comprising gate stack GS1 and gate insulator GI1, and word line WL3, comprising gate stack GS3 and gate insulator GI3, which are passive word lines for the select transistor of the trench capacitor GK2, run parallel and adjacent to the word line WL2. These word lines WL1, WL3 serve to drive select transistors, which are offset in the third dimension with respect to the sectional illustration shown.
It can be seen from FIG. 1 that this type of one-sided connection of the buried contact allows the trenches and the adjacent source regions or drain regions of corresponding select transistors to be arranged directly next to one another. This means that the length of a memory cell can be just 4F and the width just 2F, where F is the minimum length unit which is technically feasible (cf. FIG. 2a, b).
FIG. 2A shows a plan view of a first possible arrangement of a memory cell array comprising memory cells as shown in FIG. 1.
Reference symbol DT in FIG. 2A denotes trenches which are arranged in rows with a distance of 3F between them and in columns with a distance 2F between them. Adjacent cells are offset by 2F with respect to one another. UC in FIG. 2a denotes the area of a unit cell, which amounts to 4F×2F=8F2. STI denotes isolation trenches which are arranged at a distance of 1F from one another in the row direction and isolate adjacent active areas from one another. Bit lines BL also run in the row direction, with a distance of 1F between them, whereas the word lines run at a distance of 1F from one another in the column direction. In this example, all the trenches DT have a contact region KS of the buried contact to the substrate on the left-hand side and an insulation region IS on the right-hand side (regions 15a, b and 16a, b, respectively, in FIG. 1).
FIG. 2B shows a second possible arrangement of a memory cell array with memory cells in accordance with FIG. 1.
In this second possible arrangement, the rows of trenches have alternating connection regions and insulation regions of the buried contacts. Therefore, in the bottom row in FIG. 2b, the buried contacts are in each case provided with a contact region KS1 on the left-hand side and with an insulation region IS1 on the right-hand side. By contrast, in the row above, all trenches DT are provided with an insulation region IS2 on the left-hand side and with a contact region KS2 on the right-hand side. This arrangement alternates in the column direction.
For DRAM memory devices with trench capacitors in sub-100 nm technologies, the resistance of the trench and of the buried contact represent a major contribution to the total RC delay and therefore determine the speed of the DRAM. The series resistance in the trench increases dramatically as a result of the relatively low conductivity and the pinch-off which is produced by an overlay shift of the STI etch.
This problem has been addressed by the introduction of highly arsenic-doped polysilicon, an improvement to the overlay between the active areas and the trench, the introduction of a self-aligned fabrication of a buried contact with connection on one side, and thinning of the nitrided contact location of the buried contact. Nevertheless, the SiN interface significantly increases the series resistance.
It would in principle be possible to use metals such as TiN for the buried contact with connection on one side. Nevertheless, this gives the problem of incorporating large quantities of metal in the immediate vicinity of electrically active components, such as for example select transistors.